1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device having a conductive region formed to be in contact with an isolation insulator and an interconnection film contacted with the conductive region through an interlayer insulating film.
2. Description of the Prior Art
Typically, a semiconductor device has a diffusion region formed in an active region of a semiconductor substrate. The diffusion region is opposite in conductivity type to the substrate. The active region is defined by an isolation insulator formed selectively in the surface area of the substrate. An interlayer insulating film is formed to cover the diffusion region. An interconnection or wiring film having a contact hole is formed in the interlayer insulating film. The interconnection film is contacted with the underlying diffusion region through the contact hole to thereby realize electrical interconnection between the interconnection film and the diffusion region.
Conventionally, in the design process of the semiconductor device, the mask alignment for the above contact structure has been so determined that the contact hole is surely located on the diffusion region by giving sufficient values to the alignment margins.
Recently, with the decreasing dimension caused by progress in microfabrication technology, the integration level of the semiconductor devices on the substrate has been becoming higher and higher. To cope with this tendency, it has become indispensable for the mask alignment margins to decrease to a level as small as possible.
However, the decrease of the mask alignment margins causes various problems and as a result, it is essential to improve the contact structure and to develop fabrication processes realizing the improved structure.
Although a large number of semiconductor devices are produced and integrated on the semiconductor substrate, only one of the devices is explained in this specification for the sake of simplification of description.
FIGS. 1A to 1D show a first example of the conventional fabrication methods of a semiconductor device, respectively.
First, a pad oxide (SiO.sub.2) film 102 is formed on a surface of a p-silicon substrate 101. A silicon nitride (Si.sub.3 N.sub.4) film 103 is formed on the film 102, and is patterned to have a specified plan shape. Using this patterned film 103 as a mask, an p-type dopant is selectively ion-implanted into the substrate 101 to form a channel stop region 104.
Then, using this patterned silicon nitride film 103 as a mask, the surface of the substrate 101 is selectively oxidized by a thermal oxidation process, thereby producing a field oxide film 105 serving as an isolation insulator for defining active regions. The field oxide film 105 constitutes an isolation region. The state at this stage is shown in FIG. 1A.
Subsequently, the silicon nitride film 103 and the pad oxide film 102 are removed and then as shown in FIG. 1B, a gate oxide film 106 for a metal-oxide-semiconductor field-effect transistor (MOSFET) is selectively formed on the surface of the active region. A gate electrode 107a for the MOSFET is selectively formed on the gate oxide film 106.
Using the field oxide film 105 and the gate electrode 107a as a mask, an n-type dopant is ion-implanted into the substrate 101 and is followed by an annealing process, thereby producing an n-diffusion region 108 in the active region, as shown in FIG. 1B. This region 108 serves as a source/drain region of the MOSFET.
Further, an interlayer insulating film 109 is deposited to cover the active region and the field oxide film 105 over the entire substrate 101. A patterned resist film 110 with a penetrating window 111 is formed on the interlayer insulating film 109, as shown in FIG. 1C.
Using the patterned resist film 110 as a mask, the underlying interlayer insulating film 109 is selectively etched. Thus, a contact hole 112 exposing the surface of the substrate 101 is produced in the film 109, as shown in FIG. 1D. The resist film 110 is then removed.
Finally, as shown in FIGS. 2 and 3, an aluminum (Al) alloy film 113 is formed on the interlayer insulator film 109. The film 113 is then patterned to thereby produce an interconnection or wiring film. The interconnection film 113 is contacted with the underlying n-type diffusion region 108 through the contact hole 112.
If the mask alignment error exceeds the specified alignment margin during the process of forming the contact hole 112, the opposing edge of the field oxide film 105 to the diffusion region (source/drain region) 108 is also etched, as shown in FIG. 1D. As a result, the interconnection film 113 is contacted with the substrate 101 itself at a position 129 outside the diffusion region 108. This means that the interconnection film 113 and the substrate 101 are in short-circuit.
A similar problem to the above occurs in a semiconductor device with the trench isolation structure. Although various types of the trench isolation structures have been developed, only one of them is shown here.
FIGS. 4A to 4I show a second example of the conventional fabrication methods of a semiconductor device, respectively, which was disclosed in IEDM Technical Digest, pp57-60, 1993.
First, a pad oxide film 202 is formed on a surface of a p-silicon substrate 201. A silicon nitride film 203 is then formed on the film 202. Using a masking film (not shown), the surface area of the substrate 201 is selectively etched together with the films 202 and 203, thereby producing a trench 214 having a specified plan shape and a specified depth in the substrate 201.
Next, as shown in FIG. 4B, a silicon oxide film 215 is formed on the inner surface of the trench 214 by a thermal oxidation process. Boron is selectively ion-implanted into the substrate 201 through the film 215, thereby forming a p-type ion-implantation region 216.
A silicon dioxide film 217 is deposited on the silicon nitride film 203 and in the trench 217. The film 217 is then removed except for the inside of the trench 214 by a planarization process such as a chemical mechanical polishing (CMP) process. Thus, the trench 214 is filled with the remaining dioxide film 217. At the same time, the surfaces of the films 203 and 217 are planarized, as shown in FIG. 4C.
Thereafter, the silicon nitride film 203 is removed. At this stage, the top of the silicon dioxide film 217 becomes higher than the pad oxide film 202. A pair of sidewall spacers 228 made of silicon dioxide are formed on the film 202 at each side of the film 217, as shown in FIG. 4D.
The remaining pad oxide film 202 and the pair of sidewall spacers 228 are selectively removed by a wet etching process, thereby producing an isolation insulator made of the buried silicon dioxide film 217 in the trench 214, as shown in FIG. 4E. The isolation insulator defines an active region.
Subsequently, as shown in FIG. 4F, the implanted boron ions are annealed to thereby form a channel stop region 204 below the trench 214. The region 204 surrounds the bottom and side faces of the trench 214. Then, a gate oxide film 206 for a MOSFET is selectively formed on the surface of the active region. A gate electrode 207a for the MOSFET is selectively formed on the gate oxide film 206.
Using the isolation oxide film 217 and the gate electrode 207a as a mask, an n-type dopant is ion-implanted into the substrate 201, thereby producing an n-diffusion region 208 in the active region, as shown in FIG. 4F. This region 208 serves as a source/drain region of the MOSFET.
Further, an interlayer insulating film 209 is deposited to cover the active region and the isolation oxide film 217 over the entire substrate 201. A patterned resist film 210 with a penetrating window 211 is formed on the interlayer insulating film 209, as shown in FIG. 4G.
Using the patterned resist film 210 as a mask, the underlying interlayer insulating film 209 is selectively etched. Thus, a contact hole 212 exposing the surface of the substrate 201 is produced in the film 209, as shown in FIG. 4H. The resist film 210 is then removed.
Finally, as shown in FIG. 4I, an aluminum-alloy film 213 is formed on the interlayer insulator film 209 and in the contact hole 212. The film 213 is then patterned to thereby produce an interconnection or wiring conductor film. The interconnection film 213 is contacted with the underlying n-type diffusion region 208 through the contact hole 212.
If the mask alignment error exceeds the specified alignment margin during the process of forming the contact hole 212, the opposing edge of the insulating film 217 to the diffusion region (source/drain region) 208 and the corresponding part of the silicon dioxide film 215 are also etched, as shown in FIG. 4H. As a result, the interconnection film 213 is contacted with the exposed substrate 201 itself at a position 229 outside the diffusion region 208. This means that the interconnection film 213 and the substrate 201 are in short-circuit.
To solve the above problem, an improved fabrication method was developed as shown in FIGS. 5A to 5G, which was disclosed in the Japanese Non-Examined Patent Publication No. 62-130523 published in 1987.
First, a pad oxide film 302 with a thickness of 20 nm is formed on a surface of a p-silicon substrate 301. A silicon nitride film (as an oxidation-resistant film) 303 with a thickness of 100 nm is formed on the film 302. The film 303 is then patterned to have a specified plan shape. Using this patterned film 303 as a mask, the surface of the substrate 301 is selectively oxidized by a thermal oxidation process, thereby producing a field oxide film 305 defining an active region. The field oxide film 305 constitutes an isolation insulator. The state at this stage is shown in FIG. 5A.
Subsequently, without removing the silicon nitride film 303 and the pad oxide film 302, a silicon dioxide film 318 with a thickness of 100 nm to 200 nm is formed over the entire substrate 301 by a chemical vapor deposition (CVD) process, as shown in FIG. 5B.
Then, the film 318 is removed over the entire substrate 301 by a reactive ion etching (RIE) process. Thus, the film 318 is selectively left at the end 303a of the film 303 over the field oxide film 305, as shown in FIG. 5C.
The silicon nitride film 303 and the pad oxide film 302 are selectively removed by a RIE process, thereby exposing the surface of the active region of the substrate 301, as shown in FIG. 5D.
Thereafter, a gate oxide film 306 for a MOSFET is selectively formed on the exposed surface of the active region by a thermal oxidation process. The film 306 has a thickness of 20 nm.
A polysilicon film with a thickness of 300 nm is formed on the entire substrate 301. Phosphorus (P) is doped into the polysilicon film by a thermal diffusion process. The phosphorus-doped polysilicon film is patterned by a RIE process, resulting in an n-type polysilicon gate electrode 307a for the MOSFET on the gate oxide film 306.
Using the gate electrode 307a and the field oxide film 305 as a mask, an n-type dopant such as arsenic (As) is selectively ion-implanted into the substrate 301 at a dose of 5.times.10.sup.15 atoms/cm.sup.2 with an acceleration energy of 70 keV. Following this, the substrate 301 is annealed at a temperature of 940.degree. C. for 20 minutes. Thus, an n-diffusion region 308 serving as a source/drain region of the MOSFET in the active region, as shown in FIG. 5E.
Further, a silicon nitride film 319 with a thickness of 50 nm and an AsSG film 309 with a thickness of 500 nm are successively formed to cover the active and isolation regions over the entire substrate 301. Then, a patterned resist film 320 with a penetrating window 311 is formed on the AsSG film 309, as shown in FIG. 5F.
Using the patterned resist film 320 as a mask, the underlying films 309 and 319 are selectively etched by a RIE process until the diffusion region 308 is exposed. Thus, a contact hole 312 exposing the surface of the substrate 301 is produced in the films 309 and 319, as shown in FIG. 5G. During this RIE process, the remaining silicon nitride film 303 on the field oxide film 305 serves as an etching stop, and as a result, the end of the film 305 is ensured to be protected by the film 303 from the etching action. The resist film 320 is then removed. The state at this stage is shown in FIG. 5G.
Finally, an interconnection film (not shown) is formed on the AsSG film 309 to be contacted with the diffusion region 308 in the subsequent processes. These process are performed by the same manner as above.
With the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 62-130523, because of the etching stop action of the remaining silicon nitride film 303 on the field oxide film 305, the film 305 can be effectively prevented from being etched. Thus, the exposure of the substrate 301 can be avoided at a position below the end of the film 305. This means that no short-circuit between the interconnection film and the substrate 301 itself takes place outside the diffusion region 308.
However, with the conventional method of the Japanese Non-Examined Patent Publication No. 62-130523, the following problems occur.
First, it is difficult to control the lateral width of the remaining silicon nitride film 303 on the field oxide film 305 because this film 303 is obtained during the selective etching process as shown in FIG. 5C.
In consideration with further miniaturization of the semiconductor devices on the substrate 301, it is preferred that the width of the silicon nitride film 303 is as narrow as possible. On the other hand, the film 303 must cover or overlap the periphery of the active region. Accordingly, the mask alignment margin for the process of patterning the film 303 needs to be sufficiently large. In other words, the contact area between the diffusion region 308 and the interconnection film varies or fluctuates within a wide range dependent upon the alignment errors which have been generated during the patterning process of the film 303 and the formation process of the contact hole 312. This leads to obstruction or barrier for further miniaturization and integration of the semiconductor devices.
Second, when the width of the remaining silicon nitride film 303 is made narrow, (i.e., the bird's beak of the field oxide film 305 is made small), there arises a possibility of contact between the interconnection film and the substrate 301. The reason is that the etching stop function cannot be obtained sufficiently if the position of the contact hole 312 is shifted so that the contact hole 312 contains the film 303 therein.
Third, since the remaining film 303 increases the offset or step on the surface of the substrate 301, it is not suitable for the multilevel interconnection structure. Especially during the RIE process for forming the gate electrode 307a, the polysilicon film for the gate electrode 307a tends to be left in the vicinity of the film 303, which increases the danger of short-circuit between the adjoining MOSFETs.